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公开(公告)号:US12066926B2
公开(公告)日:2024-08-20
申请号:US17861084
申请日:2022-07-08
Applicant: Arm Limited
Inventor: Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan
IPC: G06F12/02
CPC classification number: G06F12/023 , G06F2212/1008
Abstract: According to one implementation of the present disclosure, an integrated circuit includes comparator circuitry coupled to peripheral circuitry of a multiport memory and configured to transmit one or more data input signals or one or more write enable signals to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory. In another implementation, a method comprises: detecting a read operation and a write operation to a same memory bitcell of a multiport memory in one clock cycle and in response to the detection, performing the read operation of a data input signal or a write enable signal of the multiport memory.
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公开(公告)号:US20230411351A1
公开(公告)日:2023-12-21
申请号:US17752560
申请日:2022-05-24
Applicant: Arm Limited
Inventor: Andy Wangkun Chen , Yew Keong Chong , Sriram Thyagarajan , Vivek Asthana , Ettore Amirante
IPC: H01L25/065 , H01L25/18 , H01L23/48 , H01L23/532 , H01L21/768 , H01L25/00
CPC classification number: H01L25/0657 , H01L25/18 , H01L23/481 , H01L2225/06541 , H01L21/76898 , H01L25/50 , H01L23/53228
Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.
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公开(公告)号:US11831341B2
公开(公告)日:2023-11-28
申请号:US17001580
申请日:2020-08-24
Applicant: Arm Limited
Inventor: Shardendu Shekhar , Andy Wangkun Chen , Yew Keong Chong
IPC: H03M7/00 , H03K19/0944 , H03K19/20 , H03K19/21 , H03M7/30
CPC classification number: H03M7/005 , H03K19/0944 , H03K19/20 , H03K19/215 , H03M7/6011
Abstract: A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.
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公开(公告)号:US11670363B2
公开(公告)日:2023-06-06
申请号:US17238683
申请日:2021-04-23
Applicant: Arm Limited
Inventor: Rahul Mathur , Mudit Bhargava , Andy Wangkun Chen
IPC: G11C5/06 , G11C11/4093 , G11C11/4094 , G11C11/408
CPC classification number: G11C11/4093 , G11C5/06 , G11C11/4085 , G11C11/4094
Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.
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公开(公告)号:US11569219B2
公开(公告)日:2023-01-31
申请号:US17077532
申请日:2020-10-22
Applicant: Arm Limited
Inventor: Rahul Mathur , Xiaoqing Xu , Andy Wangkun Chen , Mudit Bhargava , Brian Tracy Cline , Saurabh Pijuskumar Sinha
IPC: H01L27/02 , G06F30/31 , H01L21/768 , H01L23/535 , H01L25/065 , H01L25/00
Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.
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公开(公告)号:US11568926B2
公开(公告)日:2023-01-31
申请号:US17101610
申请日:2020-11-23
Applicant: Arm Limited
Inventor: Andy Wangkun Chen , Teresa Louise McLaurin , Frank David Frederick , Richard Slobodnik , Yew Keong Chong
IPC: G11C11/00 , G11C11/419 , G11C7/22 , H03K19/1776 , G11C7/10
Abstract: Various implementations described herein are directed to an integrated circuit having first latch circuitry with multiple first latches that latch multiple input data signals. The integrated circuit may include second latch circuitry having a single second latch that receives the latched multiple input data signals from the multiple first latches and outputs a single latched data signal based on the latched multiple input data signals. The integrated circuit may include intermediate logic circuitry that is coupled between the first latch circuitry and the second latch circuitry. The intermediate logic circuitry may receive and combine the multiple input data signals from the first latch circuitry into a single data signal that is provided to the single second latch of the second latch circuitry for output as the single latched data signal.
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公开(公告)号:US20230016339A1
公开(公告)日:2023-01-19
申请号:US17375887
申请日:2021-07-14
Applicant: Arm Limited
Inventor: Yew Keong Chong , Andy Wangkun Chen , Bikas Maiti , Vivek Nautiyal
Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.
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公开(公告)号:US11557583B2
公开(公告)日:2023-01-17
申请号:US17017551
申请日:2020-09-10
Applicant: Arm Limited
Inventor: Andy Wangkun Chen , Sriram Thyagarajan , Yew Keong Chong , Sony
IPC: H01L27/02 , H01L27/092 , G06F30/3953 , G06F30/392 , H01L23/48
Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.
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公开(公告)号:US20220310144A1
公开(公告)日:2022-09-29
申请号:US17209876
申请日:2021-03-23
Applicant: Arm Limited
Inventor: Akash Bangalore Srinivasa , Andy Wangkun Chen , Yew Keong Chong , Sreebin Sreedhar , Balaji Ravikumar , Penaka Phani Goberu , Vibin Vincent
IPC: G11C8/08
Abstract: Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.
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公开(公告)号:US20220223514A1
公开(公告)日:2022-07-14
申请号:US17149145
申请日:2021-01-14
Applicant: Arm Limited
Inventor: Rajiv Kumar Sisodia , Andy Wangkun Chen
IPC: H01L23/528 , H01L27/11 , H01L27/092 , H01L23/522 , H01L21/8238
Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.
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