Invention Grant
US09281198B2 Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes
有权
制造包括嵌入晶体背栅极偏置平面的半导体器件的方法
- Patent Title: Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes
- Patent Title (中): 制造包括嵌入晶体背栅极偏置平面的半导体器件的方法
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Application No.: US13900808Application Date: 2013-05-23
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Publication No.: US09281198B2Publication Date: 2016-03-08
- Inventor: Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Raghavasimhan Sreenivasan
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GlobalFoundries, Inc.
- Current Assignee: GlobalFoundries, Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Anthony J. Canale
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/84 ; H01L29/786 ; H01L27/12
Abstract:
A method of forming a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a set of bias lines on the first dielectric layer; covering the set of bias lines with a second dielectric layer; forming a semiconductor layer on the second dielectric layer; and forming a set of devices on the semiconductor layer above the set of bias lines.
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Information query
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