Invention Grant
US09281296B2 Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
有权
BGA内存封装中的芯片堆叠技术,用于小尺寸CPU和内存主板设计
- Patent Title: Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
- Patent Title (中): BGA内存封装中的芯片堆叠技术,用于小尺寸CPU和内存主板设计
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Application No.: US14448040Application Date: 2014-07-31
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Publication No.: US09281296B2Publication Date: 2016-03-08
- Inventor: Zhuowen Sun , Yong Chen , Kyong-Mo Bang
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L25/00
- IPC: H01L25/00 ; H01L25/065 ; H01L23/498 ; H01L23/00

Abstract:
A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.
Public/Granted literature
- US20160035703A1 DIE STACKING TECHNIQUES IN BGA MEMORY PACKAGE FOR SMALL FOOTPRINT CPU AND MEMORY MOTHERBOARD DESIGN Public/Granted day:2016-02-04
Information query
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