Invention Grant
US09281831B2 Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC
有权
数字提取和校正管道ADC中残留放大器的线性度
- Patent Title: Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC
- Patent Title (中): 数字提取和校正管道ADC中残留放大器的线性度
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Application No.: US14201624Application Date: 2014-03-07
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Publication No.: US09281831B2Publication Date: 2016-03-08
- Inventor: Herve Marie , Arnaud Biallais
- Applicant: Integrated Device Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Hayes and Boone LLP.
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/00 ; H03M1/18

Abstract:
Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.
Public/Granted literature
- US20150256189A1 DIGITAL EXTRACTION AND CORRECTION OF THE LINEARITY OF A RESIDUE AMPLIFIER IN A PIPELINE ADC Public/Granted day:2015-09-10
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