Invention Grant
US09287357B2 Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same
有权
具有Si和非Si纳米片FET的集成电路与低带对带隧道的协整和其制造方法
- Patent Title: Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same
- Patent Title (中): 具有Si和非Si纳米片FET的集成电路与低带对带隧道的协整和其制造方法
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Application No.: US14737048Application Date: 2015-06-11
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Publication No.: US09287357B2Publication Date: 2016-03-15
- Inventor: Mark S. Rodder , Borna Obradovic , Rwik Sengupta , Dharmendar Reddy Palle , Robert C. Bowen
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel & Sibley, P.A.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/20 ; H01L27/092 ; B82Y10/00
Abstract:
An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.
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