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公开(公告)号：US20170200499A1
公开(公告)日：2017-07-13
申请号：US15265825
申请日：2016-09-14
发明人： Titash Rakshit , Borna Obradovic
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , G11C14/00 , H01L43/04 , H01L43/06 , H01L43/08 , H01L43/10
摘要： A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.
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公开(公告)号：US09960232B2
公开(公告)日：2018-05-01
申请号：US15340775
申请日：2016-11-01
发明人： Borna Obradovic , Titash Rakshit , Mark Rodder
IPC分类号： H01L29/00 , H01L29/06 , H01L29/417 , H01L29/08 , H01L29/20 , H01L29/10 , H01L29/786 , H01L29/66 , H01L21/306 , H01L29/423
CPC分类号： H01L29/0665 , H01L21/30612 , H01L29/0847 , H01L29/1033 , H01L29/20 , H01L29/205 , H01L29/267 , H01L29/41758 , H01L29/42392 , H01L29/66522 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66742 , H01L29/7783 , H01L29/78621 , H01L29/78681
摘要： A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.
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公开(公告)号：US20170323941A1
公开(公告)日：2017-11-09
申请号：US15340775
申请日：2016-11-01
发明人： Borna Obradovic , Titash Rakshit , Mark Rodder
IPC分类号： H01L29/06 , H01L29/786 , H01L29/66 , H01L29/417 , H01L29/20 , H01L29/10 , H01L29/08 , H01L21/306
CPC分类号： H01L29/0665 , H01L21/30612 , H01L29/0847 , H01L29/1033 , H01L29/20 , H01L29/205 , H01L29/267 , H01L29/41758 , H01L29/42392 , H01L29/66522 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66742 , H01L29/7783 , H01L29/78621 , H01L29/78681
摘要： A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, and a channel region under the gate electrode and extending between the source electrode and the drain electrode. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The hNS FET also includes at least one layer of crystalline barrier material having a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region.
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公开(公告)号：US09647098B2
公开(公告)日：2017-05-09
申请号：US14593636
申请日：2015-01-09
IPC分类号： H01L29/66 , H01L29/16 , H01L29/20 , H01L29/10 , H01L29/161 , H01L29/739 , H01L29/06 , H01L21/311 , H01L21/22 , H01L29/78
CPC分类号： H01L29/66977 , H01L21/823412 , H01L21/823418 , H01L21/8252 , H01L27/0605 , H01L27/0688 , H01L27/088 , H01L29/0673 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/205 , H01L29/7391
摘要： A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.
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5.发明授权Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same 有权具有Si和非Si纳米片FET的集成电路与低带对带隧道的协整和其制造方法公开(公告)号：US09287357B2
公开(公告)日：2016-03-15
申请号：US14737048
申请日：2015-06-11
IPC分类号： H01L29/06 , H01L29/20 , H01L27/092 , B82Y10/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y40/00 , H01L21/8258 , H01L27/092 , H01L27/0924 , H01L29/0673 , H01L29/16 , H01L29/20 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , Y10S977/755
摘要： An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.
摘要翻译： 集成电路可以包括多个第一，非Si，纳米片状场效应晶体管（FET）和多个第二，Si，纳米片FET。 第一非硅纳米片FET的纳米片可以包括少于约30％的Si。 第一个非Si纳米片FET可以限定集成电路的电路的临界速度路径。 第二，Si，纳米片FET的纳米片可以包括大于约30％的Si。 第二个Si纳米片FET可以定义集成电路的非临界速度路径。 第一非硅纳米片FET的结构可以被配置为具有比第二Si纳米片FET的速度更高的速度。
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公开(公告)号：US09899529B2
公开(公告)日：2018-02-20
申请号：US15195886
申请日：2016-06-28
发明人： Joon Goo Hong , Borna Obradovic , Mark Rodder
IPC分类号： H01L21/22 , H01L29/786 , H01L29/423 , H01L29/06 , H01L29/66 , H01L21/225
CPC分类号： H01L29/78642 , H01L21/2256 , H01L29/0676 , H01L29/42392 , H01L29/66666 , H01L29/66742 , H01L29/66772 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.
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公开(公告)号：US09653287B2
公开(公告)日：2017-05-16
申请号：US14919634
申请日：2015-10-21
发明人： Mark Rodder , Joon Hong , Jorge Kittl , Borna Obradovic
IPC分类号： H01L21/02 , H01L29/417 , H01L29/786 , H01L29/45 , H01L29/66 , H01L29/06 , H01L21/285
CPC分类号： H01L21/02603 , H01L21/28518 , H01L21/28531 , H01L29/0665 , H01L29/41733 , H01L29/41758 , H01L29/45 , H01L29/66742 , H01L29/78696
摘要： A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.
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公开(公告)号：US20170077304A1
公开(公告)日：2017-03-16
申请号：US15132960
申请日：2016-04-19
发明人： Borna Obradovic , Chris Bowen , Titash Rakshit , Palle Dharmendar , Mark Rodder
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7842 , H01L21/28247 , H01L21/823487 , H01L29/42392 , H01L29/66522 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/78642 , H01L29/78681 , H01L29/78696
摘要： A vertical field effect device includes a substrate and a vertical channel including InxGa1-xAs on the substrate. The vertical channel includes a pillar that extends from the substrate and includes opposing vertical surfaces. The device further includes a stressor layer on the opposing vertical surfaces of the vertical channel. The stressor layer includes a layer of epitaxial crystalline material that is epitaxially formed on the vertical channel and that has lattice constant in a vertical plane corresponding to one of the opposing vertical surfaces of the vertical channel that is greater than a corresponding lattice constant of the vertical channel.
摘要翻译： 垂直场效应器件包括衬底和在衬底上包括In x Ga 1-x As的垂直沟道。 垂直通道包括从基板延伸并包括相对的垂直表面的支柱。 该装置还包括在垂直通道的相对的垂直表面上的应力层。 应力层包括外延形成在垂直通道上的外延晶体材料层，并且在垂直平面中具有与垂直沟道的相对垂直表面中的一个相垂直的晶格常数的晶格常数大于垂直沟道的对应晶格常数 渠道。
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公开(公告)号：US09870940B2
公开(公告)日：2018-01-16
申请号：US15066177
申请日：2016-03-10
发明人： Wei-E Wang , Mark Rodder , Borna Obradovic
IPC分类号： H01L21/762 , H01L21/311 , H01L21/322 , H01L21/306
CPC分类号： H01L21/76251 , H01L21/02002 , H01L21/306 , H01L21/31105 , H01L21/31116 , H01L21/31122 , H01L21/3226
摘要： Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
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公开(公告)号：US09805795B2
公开(公告)日：2017-10-31
申请号：US15265825
申请日：2016-09-14
发明人： Titash Rakshit , Borna Obradovic
IPC分类号： G11C11/00 , G11C14/00 , G11C11/18 , G11C11/16 , H01L43/08 , H01L43/04 , H01L43/06 , H01L43/10
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/18 , G11C14/00 , H01L43/04 , H01L43/06 , H01L43/08 , H01L43/10
摘要： A non-volatile data retention circuit, which is configured to store complementary volatile charge states of an external latch, comprises a coupled giant spin hall latch configured to generate and store complementary non-volatile spin states corresponding to the complementary volatile charge states of the external latch in response to receiving a charge current from the external latch, and to generate a differential charge current signal corresponding to the complementary non-volatile spin states in response to application of a read voltage, a write switch coupled to the coupled giant spin hall latch and configured to selectively enable flow of the charge current from the external latch to the coupled giant spin hall latch in response to a sleep signal, and a read switch coupled to the coupled giant spin hall latch and to selectively enable the application of the read voltage to the coupled giant spin hall latch.
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