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    INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME 有权
    包含应变通道区域的集成电路装置及其形成方法

    公开(公告)号：US20150123075A1

    公开(公告)日：2015-05-07

    申请号：US14304008

    申请日：2014-06-13

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ryan M. Hatcher ,  Mark S. Rodder ,  Robert C. Bowen ,  Jorge A. Kittl

    IPC分类号： H01L29/10 ,  H01L29/15 ,  H01L29/78

    CPC分类号： H01L29/7781 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/122 ,  H01L29/22 ,  H01L29/267 ,  H01L29/66431 ,  H01L29/785

    摘要： Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness TW sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

    摘要翻译： 提供包括应变通道区域的集成电路器件及其形成方法。 集成电路器件可以包括增强型场效应晶体管。 增强型场效应晶体管可以包括具有足够的阱厚度TW的量子阱沟道区，其足以产生其中的多个等效电子传导状态的应变引起的分裂到相应的不等能级，包括与 当表面被偏置到反转状态时，邻近通道区域的表面的最低表面粗糙度散射。

    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET
    4.
    发明申请
    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET 有权
    应变堆叠的纳米晶体管和/或量子堆积的纳米硅片

    公开(公告)号：US20160111337A1

    公开(公告)日：2016-04-21

    申请号：US14887484

    申请日：2015-10-20

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ryan M. Hatcher ,  Robert C. Bowen ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

    IPC分类号： H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L21/02

    CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/22 ,  H01L29/42392 ,  H01L29/66484 ,  H01L29/775 ,  H01L29/7847

    摘要： Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

    摘要翻译： 示例性实施例提供制造双轴应变纳米片。 示例性实施例的方面包括：生长具有一个或多个周期的外延晶体初始超晶格，每个周期包括至少三个层，活性材料层，第一牺牲材料层和第二牺牲材料层，第一和第二 具有不同材料特性的牺牲材料层; 在一个或多个周期的每一个中，将每个活性材料层放置在第一和第二牺牲材料层之间，其中第一和第二牺牲材料层的晶格常数不同于活性材料层并且在活性物质层中施加双轴应力 材料层; 选择性地蚀刻掉所有的第一牺牲材料层，从而暴露活性材料的一个表面以进行附加处理，同时活性材料层中的双轴应变由第二牺牲材料层保持; 并且选择性地蚀刻掉所有第二牺牲材料层，从而暴露活性材料层的第二表面用于额外的处理。

    CONFINED SEMI-METAL FIELD EFFECT TRANSISTOR
    8.
    发明申请
    CONFINED SEMI-METAL FIELD EFFECT TRANSISTOR 有权
    限制半金属场效应晶体管

    公开(公告)号：US20160071970A1

    公开(公告)日：2016-03-10

    申请号：US14625376

    申请日：2015-02-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

    IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/66

    CPC分类号： H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

    摘要： Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

    摘要翻译： 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。

    METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS
    10.
    发明申请
    METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS 有权
    制备具有多层掺杂层的量子阱效应晶体管的方法

    公开(公告)号：US20140329374A1

    公开(公告)日：2014-11-06

    申请号：US13947239

    申请日：2013-07-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： Mark S. Rodder ,  Robert C. Bowen

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66469 ,  H01L29/66795 ,  H01L29/7784 ,  H01L29/785

    摘要： Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

    摘要翻译： 提供了量子阱场效应晶体管的制造方法。 所述方法可以包括在量子阱层上形成包括第一δ掺杂层的第一势垒层，并且在衬底的第一区域中在第一势垒层的一部分上选择性地形成包括第二δ掺杂层的第二阻挡层。 所述方法还可以包括图案化第一和第二阻挡层和量子阱层，以在第一区域中形成第一量子阱沟道结构，并且对第一势垒层和量子阱层进行构图以形成第二量子阱沟道结构 第二区。 该方法还可以包括在衬底的第一和第二量子阱沟道结构上形成栅极绝缘层，并在栅极绝缘层上形成栅极电极层。