Invention Grant
- Patent Title: Display having vertical gate line extensions and minimized borders
- Patent Title (中): 显示屏具有垂直门线延伸和最小边界
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Application No.: US14504215Application Date: 2014-10-01
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Publication No.: US09293102B1Publication Date: 2016-03-22
- Inventor: Hao-Lin Chiu , Byung Duk Yang , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang , Szu-Hsien Lee
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple, Inc.
- Current Assignee: Apple, Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Treyz Law Group, P.C.
- Agent G. Victor Treyz; Joseph F. Guihan
- Main IPC: G09G3/36
- IPC: G09G3/36 ; H01L27/12 ; H01L23/522 ; H01L23/528 ; G02F1/1368 ; G02F1/1362

Abstract:
A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
Public/Granted literature
- US20160098965A1 Display Having Vertical Gate Line Extensions and Minimized Borders Public/Granted day:2016-04-07
Information query
IPC分类: