Invention Grant
US09293204B2 Non-volatile memory cell with self aligned floating and erase gates, and method of making same
有权
具有自对准浮动和擦除栅极的非易失性存储单元及其制造方法
- Patent Title: Non-volatile memory cell with self aligned floating and erase gates, and method of making same
- Patent Title (中): 具有自对准浮动和擦除栅极的非易失性存储单元及其制造方法
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Application No.: US14252929Application Date: 2014-04-15
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Publication No.: US09293204B2Publication Date: 2016-03-22
- Inventor: Nhan Do , Jinho Kim , Xian Liu
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L27/115 ; G11C16/04 ; G11C16/14 ; H01L29/66 ; H01L29/423
Abstract:
A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.
Public/Granted literature
- US20140307511A1 Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same Public/Granted day:2014-10-16
Information query
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