公开(公告)号：US11183506B2

公开(公告)日：2021-11-23

申请号：US17005139

申请日：2020-08-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Xian Liu ,  Feng Zhou ,  Parviz Ghazavi ,  Steven Lemke ,  Nhan Do

IPC: H01L27/11536 ,  H01L29/66 ,  H01L21/3205 ,  H01L27/11521 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/321

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

公开(公告)号：US10797142B2

公开(公告)日：2020-10-06

申请号：US16208288

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3105 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

公开(公告)号：US10790292B2

公开(公告)日：2020-09-29

申请号：US16057749

申请日：2018-08-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Xian Liu ,  Feng Zhou ,  Parviz Ghazavi ,  Steven Lemke ,  Nhan Do

IPC: H01L27/11521 ,  H01L21/027 ,  H01L27/11536 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/265 ,  H01L21/321

Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.

公开(公告)号：US09633735B2

公开(公告)日：2017-04-25

申请号：US14486687

申请日：2014-09-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Nhan Do ,  Yuri Tkachev ,  Kai Man Yue ,  Xiaozhou Qian ,  Ning Bai

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/12 ,  G11C29/02

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

公开(公告)号：US09418744B2

公开(公告)日：2016-08-16

申请号：US14275362

申请日：2014-05-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Anh Ly ,  Victor Markov

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C8/10 ,  G11C7/02 ,  G11C16/14

CPC classification number: G11C16/14 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/3427

Abstract: An improved control gate decoding design may reduce disturbances during the programming of flash memory cells. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.

Abstract translation: 改进的控制门解码设计可以减少在闪速存储器单元的编程期间的干扰。 在一个实施例中，控制栅极线解码器耦合到与第一扇区中的一行闪存单元相关联的第一控制栅极线和耦合到与第二扇区中的一行闪存单元相关联的第二控制栅极线。

公开(公告)号：US20200013788A1

公开(公告)日：2020-01-09

申请号：US16422740

申请日：2019-05-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L27/11524 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L21/266 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

公开(公告)号：US20140307511A1

公开(公告)日：2014-10-16

申请号：US14252929

申请日：2014-04-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Jinho Kim ,  Xian Liu

IPC: H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  H01L29/66

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7889

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.

Abstract translation: 存储器件及其制造方法，其中将沟槽形成为半导体材料的衬底。 源极区形成在沟槽下方，并且源极和漏极区域之间的沟道区域包括基本上沿着沟槽的侧壁延伸的第一部分和基本上沿着衬底的表面延伸的第二部分。 浮栅设置在沟槽中，与沟道区第一部分绝缘，用于控制其导电性。 控制栅极设置在通道区域第二部分之上并与沟道区域第二部分绝缘，以控制其导电性。 擦除栅极至少部分地布置在浮栅上并与浮栅绝缘。 导电耦合栅极设置在沟槽中，与浮动栅极相邻并与其隔离，并且与源极区域隔离并且绝缘。

公开(公告)号：US12131786B2

公开(公告)日：2024-10-29

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C5/06 ,  G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US20230290864A1

公开(公告)日：2023-09-14

申请号：US17824812

申请日：2022-05-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Serguei Jourba ,  Catherine Decobert ,  Feng Zhou ,  Jinho Kim ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11556

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/42328 ,  H01L29/7851 ,  H01L27/11556

Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.

公开(公告)号：US11018147B1

公开(公告)日：2021-05-25

申请号：US16781798

申请日：2020-02-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Catherine Decobert ,  Yuri Tkachev ,  Bruno Villard ,  Nhan Do

IPC: H01L21/00 ,  H01L27/11534 ,  H01L21/28 ,  H01L21/311 ,  H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L21/027 ,  H01L27/11521 ,  H01L29/788

Abstract: A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.