发明授权
- 专利标题: 3DIC interconnect apparatus and method
- 专利标题(中): 3DIC互连设备和方法
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申请号: US14020370申请日: 2013-09-06
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公开(公告)号: US09293392B2公开(公告)日: 2016-03-22
- 发明人: Shih Pei Chou , Hung-Wen Hsu , Ching-Chung Su , Chun-Han Tsao , Lin Chia-Chieh , Shu-Ting Tsai , Jiech-Fun Lu , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater & Matsil, L.L.P.
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L25/065 ; H01L25/00 ; H01L21/683 ; H01L25/16
摘要:
An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
公开/授权文献
- US20150069619A1 3DIC Interconnect Apparatus and Method 公开/授权日:2015-03-12
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