公开(公告)号：US20210036179A1

公开(公告)日：2021-02-04

申请号：US16865819

申请日：2020-05-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih Wei Sung ,  Chung-Bin Tseng ,  Keng-Ying Liao ,  Yen-Jou Wu ,  Po-Zen Chen ,  Su-Yu Yeh ,  Ching-Chung Su

IPC分类号： H01L31/18

摘要： A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

公开(公告)号：US10361234B2

公开(公告)日：2019-07-23

申请号：US15944069

申请日：2018-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Pei Chou ,  Hung-Wen Hsu ,  Ching-Chung Su ,  Chun-Han Tsao ,  Chia-Chieh Lin ,  Shu-Ting Tsai ,  Jiech-Fun Lu ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/683 ,  H01L25/16

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US09984918B2

公开(公告)日：2018-05-29

申请号：US15088126

申请日：2016-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ching-Chung Su ,  Jiech-Fun Lu ,  Jian Wu ,  Che-Hsiang Hsueh ,  Ming-Chi Wu ,  Chi-Yuan Wen ,  Chun-Chieh Fang ,  Yu-Lung Yeh

IPC分类号： H01L21/764 ,  H01L21/762

CPC分类号： H01L21/764 ,  H01L21/3083 ,  H01L21/76232

摘要： A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

公开(公告)号：US10163972B2

公开(公告)日：2018-12-25

申请号：US15092317

申请日：2016-04-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Hung-Wen Hsu ,  Jung-I Lin ,  Ching-Chung Su ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L27/146

摘要： A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.

公开(公告)号：US09337225B2

公开(公告)日：2016-05-10

申请号：US14026141

申请日：2013-09-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Hung-Wen Hsu ,  Jung-I Lin ,  Ching-Chung Su ,  Jiech-Fun Lu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/14623 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

摘要： A backside illumination semiconductor image sensing device includes a semiconductor substrate. The semiconductor substrate includes a radiation sensitive diode and a peripheral region. The peripheral region is proximal to a sidewall of the backside illumination semiconductor image sensing device. The backside illumination semiconductor image sensing device further includes a first anti reflective coating (ARC) on a backside of the semiconductor substrate and a dielectric layer on the first anti reflective coating. Additionally, a radiation shielding layer is disposed on the dielectric layer. Moreover, the backside illumination semiconductor image sensing device has a photon blocking layer on the sidewall of the backside illumination semiconductor image sensing device. The at least a portion of a sidewall of the radiation shielding layer is not covered by the photon blocking layer and the photon blocking layer is configured to block photons penetrating into the semiconductor substrate.

摘要翻译： 背面照明半导体图像感测装置包括半导体衬底。 半导体衬底包括辐射敏感二极管和外围区域。 外围区域靠近背侧照明半导体图像感测装置的侧壁。 背面照明半导体图像感测装置还包括在半导体衬底的背面上的第一抗反射涂层（ARC）和第一抗反射涂层上的介电层。 另外，辐射屏蔽层设置在电介质层上。 此外，背面照明半导体图像感测装置在背面照明半导体图像感测装置的侧壁上具有光子阻挡层。 辐射屏蔽层的侧壁的至少一部分未被光子阻挡层覆盖，并且光子阻挡层被配置为阻挡穿透到半导体衬底中的光子。

公开(公告)号：US09293392B2

公开(公告)日：2016-03-22

申请号：US14020370

申请日：2013-09-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Pei Chou ,  Hung-Wen Hsu ,  Ching-Chung Su ,  Chun-Han Tsao ,  Lin Chia-Chieh ,  Shu-Ting Tsai ,  Jiech-Fun Lu ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L25/16

CPC分类号： H01L27/14634 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

摘要翻译： 提供了互连装置和形成互连装置的方法。 诸如晶片，管芯或晶片和管芯之类的两个基片结合在一起。 第一掩模用于形成部分地延伸到在第一晶片上形成的互连的第一开口。 形成电介质衬垫，然后使用相同的掩模进行另一蚀刻工艺。 蚀刻工艺继续暴露形成在第一衬底和第二衬底上的互连。 开口填充有导电材料以形成导电塞。

公开(公告)号：US20180226449A1

公开(公告)日：2018-08-09

申请号：US15944069

申请日：2018-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Pei Chou ,  Hung-Wen Hsu ,  Ching-Chung Su ,  Chun-Han Tsao ,  Chia-Chieh Lin ,  Shu-Ting Tsai ,  Jiech-Fun Lu ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L27/146 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L21/683 ,  H01L25/00 ,  H01L25/16

CPC分类号： H01L27/14634 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US09941320B2

公开(公告)日：2018-04-10

申请号：US15076115

申请日：2016-03-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih Pei Chou ,  Hung-Wen Hsu ,  Ching-Chung Su ,  Chun-Han Tsao ,  Chia-Chieh Lin ,  Shu-Ting Tsai ,  Jiech-Fun Lu ,  Shih-Chang Liu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L31/00 ,  H01L27/146 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/683 ,  H01L25/16

CPC分类号： H01L27/14634 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00

摘要： An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

公开(公告)号：US11990488B2

公开(公告)日：2024-05-21

申请号：US17249787

申请日：2021-03-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Lin Chen ,  Ching-Chung Su ,  Chun-Hao Chou ,  Kuo-Cheng Lee

IPC分类号： H01L27/146 ,  H04N25/77

CPC分类号： H01L27/14621 ,  H01L27/14609 ,  H01L27/1463 ,  H04N25/77 ,  H01L27/14627

摘要： A grid structure in a pixel array may be at least partially angled or tapered toward a top surface of the grid structure such that the width of the grid structure approaches a near-zero width near the top surface of the grid structure. This permits the spacing between color filter regions in between the grid structure to approach a near-zero spacing near the top surfaces of the color filter regions. The tight spacing of color filter regions provided by the angled or tapered grid structure provides a greater surface area and volume for incident light collection in the color filter regions. Moreover, the width of the grid structure may increase at least partially toward a bottom surface of the grid structure such that the wider dimension of the grid structure near the bottom surface of the grid structure provides optical crosstalk protection for the pixel sensors in the pixel array.

公开(公告)号：US11522004B2

公开(公告)日：2022-12-06

申请号：US17002042

申请日：2020-08-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Chung Su ,  Hung-Wen Hsu ,  Jiech-Fun Lu ,  Shih-Pei Chou

IPC分类号： H01L27/146

摘要： The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. The substrate has a plurality of protrusions disposed along a first side of the substrate over the image sensing element and a ridge disposed along the first side of the substrate. The ridge continuously extends around the plurality of protrusions.