Invention Grant
US09293587B2 Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device
有权
形成嵌入式源极和漏极区域,以防止介电隔离鳍片场效应晶体管(FinFET)器件中的底部泄漏
- Patent Title: Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device
- Patent Title (中): 形成嵌入式源极和漏极区域,以防止介电隔离鳍片场效应晶体管(FinFET)器件中的底部泄漏
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Application No.: US13948374Application Date: 2013-07-23
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Publication No.: US09293587B2Publication Date: 2016-03-22
- Inventor: Ajey Poovannummoottil Jacob , Murat K. Akarvardar
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams Morgan, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L21/84 ; H01L27/12

Abstract:
Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).
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