公开(公告)号：US20210003776A1

公开(公告)日：2021-01-07

申请号：US16502667

申请日：2019-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/126

Abstract: One illustrative TE pass polarizer disclosed herein includes an input/output layer, a first buffer layer positioned above at least a portion of the input/output layer, a layer of epsilon-near-zero (ENZ) material positioned above at least a portion of the first buffer layer, and a metal-containing capping layer positioned above at least a portion of the layer of ENZ material.

公开(公告)号：US10816726B1

公开(公告)日：2020-10-27

申请号：US16549415

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bo Peng ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Thomas Houghton ,  Asli Sahin

IPC: G02B6/34 ,  G02B6/122 ,  G02B6/38 ,  G02B6/36 ,  G02B6/30

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. A waveguide core and a coupler are formed over a layer stack that includes a first dielectric layer and a second dielectric layer over the first dielectric layer. The coupler includes a first plurality of grating structures and a transition structure including a second plurality of grating structures that are positioned between the first plurality of grating structures and the waveguide core. The first plurality of grating structures include respective widths that vary as a function of position relative to the transition structure.

公开(公告)号：US10747030B1

公开(公告)日：2020-08-18

申请号：US16597310

申请日：2019-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02F1/025 ,  G02F1/035

Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. An electro-optic modulator is positioned proximate to a section of a waveguide core. The electro-optic modulator includes an active layer and a confinement layer. The active layer is composed of a first material, the confinement layer is composed of a second material with a different composition than the first material, the first material has a refractive index that is variable under an applied bias voltage, and the second material has a permittivity with an imaginary part that ranges from 0 to about 15.

公开(公告)号：US10649140B1

公开(公告)日：2020-05-12

申请号：US16291671

申请日：2019-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/13 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. A back-end-of-line interconnect structure includes a cap layer, an interlayer dielectric layer, and one or more metal features embedded in the interlayer dielectric layer. The interlayer dielectric layer is stacked in a vertical direction with the cap layer. The one or more metal features have an overlapping arrangement in a lateral direction with the waveguide core, which is arranged under the back-end-of-line interconnect structure.

公开(公告)号：US20200124796A1

公开(公告)日：2020-04-23

申请号：US16165600

申请日：2018-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/136 ,  G02B6/122

Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A first dielectric layer comprised of a first silicon nitride is formed. The waveguide is arranged over the first dielectric layer. A second dielectric layer is formed that is arranged over the waveguide. The second dielectric layer is composed of a second silicon nitride having a lower absorption of optical signals than the first silicon nitride.

公开(公告)号：US10510392B1

公开(公告)日：2019-12-17

申请号：US16047882

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bipul C. Paul ,  Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

公开(公告)号：US10436982B1

公开(公告)日：2019-10-08

申请号：US16038868

申请日：2018-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/13

Abstract: Structures including waveguide bends, methods of fabricating a structure that includes waveguide bends, and systems that integrate optical components containing different materials. A first waveguide bend is contiguous with a waveguide, and a second waveguide bend is spaced in a vertical direction from the first waveguide bend. The second waveguide bend has an overlapping arrangement with the first waveguide bend in a lateral direction.

公开(公告)号：US10429581B1

公开(公告)日：2019-10-01

申请号：US16189125

申请日：2018-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abu Thomas ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/12 ,  G02B6/126 ,  G02B6/13 ,  G02B6/293

Abstract: Structures for a polarization splitter and methods of forming a polarization splitter. A multi-mode interference region includes a first waveguide and a second waveguide arranged in a stack over the first waveguide. First and second input ports are connected with the multi-mode interference region. First and second output ports are connected with the multi-mode interference region.

公开(公告)号：US09799767B2

公开(公告)日：2017-10-24

申请号：US14940597

申请日：2015-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/7781

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.

公开(公告)号：US09716174B2

公开(公告)日：2017-07-25

申请号：US13945455

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/66795

Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET. The oxidized sacrificial layer under the active channel prevents punch-through leakage in the final FinFET structure.