Invention Grant
- Patent Title: Capacitance multiplier and loop filter noise reduction in a PLL
- Patent Title (中): PLL中的电容乘法器和环路滤波器降噪
-
Application No.: US14323794Application Date: 2014-07-03
-
Publication No.: US09294106B2Publication Date: 2016-03-22
- Inventor: Abhirup Lahiri , Nitin Gupta
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Slater & Matsil, LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/089 ; H03L7/093

Abstract:
According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.
Public/Granted literature
- US20160006442A1 Capacitance Multiplier and Loop Filter Noise Reduction in a PLL Public/Granted day:2016-01-07
Information query