Invention Grant
US09294106B2 Capacitance multiplier and loop filter noise reduction in a PLL 有权
PLL中的电容乘法器和环路滤波器降噪

Capacitance multiplier and loop filter noise reduction in a PLL
Abstract:
According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.
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