Invention Grant
US09305878B2 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
有权
用于制造在金属触点和互连之间具有覆盖层的集成电路的集成电路和方法
- Patent Title: Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
- Patent Title (中): 用于制造在金属触点和互连之间具有覆盖层的集成电路的集成电路和方法
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Application No.: US14570617Application Date: 2014-12-15
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Publication No.: US09305878B2Publication Date: 2016-04-05
- Inventor: Torsten Huisinga , Carsten Peters , Andreas Ott , Axel Preusse
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/485 ; H01L23/532 ; H01L21/768 ; H01L23/528
Abstract:
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.
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