公开(公告)号：US20150097291A1

公开(公告)日：2015-04-09

申请号：US14570617

申请日：2014-12-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a metal contact structure, an electrically conductive capping layer formed on the metal contact structure, and a conductive via electrically connected to the metal contact structure through the electrically conductive capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括金属接触结构，形成在金属接触结构上的导电覆盖层，以及通过导电覆盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US08932911B2

公开(公告)日：2015-01-13

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/4763 ,  H01L21/82 ,  H01L21/311 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US20140264641A1

公开(公告)日：2014-09-18

申请号：US14184826

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Frohberg ,  Marco Lepper ,  Katrin Reiche ,  Torsten Huisinga

IPC: H01L29/49

CPC classification number: H01L29/4175 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53247 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/05 ,  H01L29/7833 ,  H01L2224/0401 ,  H01L2924/00 ,  H01L2924/0002

Abstract: When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers.

Abstract translation: 当形成具有接触插塞的半导体器件时，其包括形成在蚀刻停止层的侧壁上的保护层以减少短路的风险，可以通过执行溅射工艺来形成保护层，以从接触区域移除材料并将去除的材料重新沉积在侧壁上 的蚀刻停止层。

公开(公告)号：US09478602B2

公开(公告)日：2016-10-25

申请号：US14507927

申请日：2014-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device comprising a capacitor structure is provided, including the steps of forming a first metallization layer comprising a first dielectric layer and a first conductive layer functioning as a lower electrode for the capacitor structure over a semiconductor substrate, forming a barrier layer functioning as a capacitor insulator for the capacitor structure on the first metallization layer, forming a metal layer on the barrier layer and etching the metal layer to form an upper electrode of the capacitor structure.

Abstract translation: 提供一种制造包括电容器结构的半导体器件的方法，包括以下步骤：在半导体衬底上形成第一金属化层，其包括第一电介质层和用作电容器结构的下电极的第一导电层，形成屏障 层作为第一金属化层上的电容器结构的电容绝缘体，在阻挡层上形成金属层，并蚀刻金属层以形成电容器结构的上部电极。

公开(公告)号：US20150076559A1

公开(公告)日：2015-03-19

申请号：US14028876

申请日：2013-09-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Kai Frohberg ,  Torsten Huisinga ,  Egon Ronny Pfuetzner

IPC: H01L29/165 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/165 ,  H01L21/76272 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649

Abstract: Integrated circuits with strained silicon and methods for fabricating such integrated circuits are provided. An integrated circuit includes a stack with a surface layer, an intermediate layer, and a base layer, where the surface layer overlies the intermediate layer, and the intermediate layer overlies the base layer. The surface layer and the base layer include strained silicon, where the silicon atoms are stretched beyond a normal crystalline silicon interatomic distance. The intermediate layer includes crystalline silicon germanium.

Abstract translation: 提供了具有应变硅的集成电路及其制造方法。 集成电路包括具有表面层，中间层和基底层的堆叠，其中表面层覆盖在中间层上，中间层覆盖在基底层上。 表面层和基层包括应变硅，其中硅原子被拉伸超过正常晶体硅原子间距离。 中间层包括晶体硅锗。

公开(公告)号：US20140239503A1

公开(公告)日：2014-08-28

申请号：US13778558

申请日：2013-02-27

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

公开(公告)号：US20150235896A1

公开(公告)日：2015-08-20

申请号：US14185398

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Oliver Mieth ,  Carsten Peters ,  Torsten Huisinga

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/3105 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76895

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使覆盖在半导体衬底之上的金属化层上的介电材料的ILD层的上表面部分致密化，以形成电介质材料的致密表面层。 蚀刻致密表面层和ILD层以暴露金属化层的金属线。

公开(公告)号：US20170005159A1

公开(公告)日：2017-01-05

申请号：US15266439

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L21/768

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.

Abstract translation: 半导体器件包括包括第一介电层的第一金属化层。 第一导电层和第一导电结构嵌入在第一介电层中。 第二介电层设置在第一金属化层上。 第二导电层设置在第二电介质层上，并且在横向上具有比横向上的第一导电层的横向尺寸更大的横向尺寸。 第三介电层设置在第二导电层上。 第一触点设置在第三电介质层中，并且在其第一外围区域中延伸穿过第二导电结构，该第一外围区域不与第一导电层重叠以接触第一导电结构。 电容器结构包括第一导电层，第二介电层和第二导电层。

公开(公告)号：US20140349479A1

公开(公告)日：2014-11-27

申请号：US13901778

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Oliver Mieth ,  Torsten Huisinga ,  Carsten Peters ,  Bernd Hintze ,  Grit Bonsdorf

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  C23F1/32 ,  C23F1/38 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution.

Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括导电特征，其包括第一金属，设置在导电特征上的介电材料和硬掩模。 硬掩模包括硬掩模材料并且设置在电介质材料上。 在层间电介质和硬掩模中设置开口。 导电特征的一部分暴露在开口的底部。 硬掩模被删除。 去除硬掩模包括将半导体结构暴露于包括过氧化氢和腐蚀抑制剂的蚀刻溶液。 在去除硬掩模之后，冲洗半导体结构。 冲洗半导体结构包括将半导体结构暴露于碱性冲洗溶液中。

公开(公告)号：US09685497B2

公开(公告)日：2017-06-20

申请号：US15266439

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert Seidel ,  Torsten Huisinga

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/7685 ,  H01L28/75

Abstract: A semiconductor device includes a first metallization layer including a first dielectric layer. A first conductive layer and a first conductive structure are embedded in the first dielectric layer. A second dielectric layer is disposed on the first metallization layer. A second conductive layer is disposed on the second dielectric layer and has a lateral dimension in a lateral direction larger than a lateral dimension of the first conductive layer in the lateral direction. A third dielectric layer is disposed on the second conductive layer. A first contact is disposed in the third dielectric layer and extends through the second conductive structure in a first peripheric region thereof that does not overlap the first conductive layer to contact the first conductive structure. A capacitor structure includes the first conductive layer, the second dielectric layer and the second conductive layer.