Invention Grant
- Patent Title: Stress-generating structure for semiconductor-on-insulator devices
- Patent Title (中): 绝缘体上半导体器件的应力产生结构
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Application No.: US13778419Application Date: 2013-02-27
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Publication No.: US09305999B2Publication Date: 2016-04-05
- Inventor: Huilong Zhu , Brian J. Greene , Dureseti Chidambarrao , Gregory G. Freeman
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L21/331
- IPC: H01L21/331 ; H01L21/8222 ; H01L29/06 ; H01L29/10 ; H01L29/84 ; H01L21/762

Abstract:
A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.
Public/Granted literature
- US20130168804A1 STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES Public/Granted day:2013-07-04
Information query
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