公开(公告)号：US10074571B1

公开(公告)日：2018-09-11

申请号：US15451869

申请日：2017-03-07

申请人： GLOBALFOUNDRIES INC.

发明人： Brian J. Greene ,  Shreesh Narasimha ,  Scott R. Stiffler

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66

摘要： A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.

公开(公告)号：US20170287829A1

公开(公告)日：2017-10-05

申请号：US15085077

申请日：2016-03-30

申请人： GLOBALFOUNDRIES INC.

发明人： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC分类号： H01L23/528 ,  H01L29/66 ,  H01L29/08 ,  H01L23/535 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/161

CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

摘要： Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US09536985B2

公开(公告)日：2017-01-03

申请号：US14499356

申请日：2014-09-29

申请人： GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Brian J. Greene ,  Eric C. T. Harley ,  Judson R. Holt ,  Yue Ke ,  Rishikesh Krishnan ,  Renee T. Mo ,  Yinxiao Yang

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L29/7848

摘要： A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

摘要翻译： 一种用于制造半导体结构的方法以及半导体结构，其使用半导体鳍周围的绝缘层的部分去除，并且随后在暴露区域中外延生长另外的半导体材料，同时保持鳍的形状，同时保持鳍的形状 绝缘层。

公开(公告)号：US09437496B1

公开(公告)日：2016-09-06

申请号：US14727219

申请日：2015-06-01

申请人： GLOBALFOUNDRIES INC.

发明人： Michael P. Chudzik ,  Brian J. Greene ,  Edward P. Maciejewski ,  Kevin McStay ,  Shreesh Narasimha ,  Chengwen Pei ,  Werner A. Rausch

IPC分类号： H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC分类号： H01L29/66795 ,  H01L29/66545

摘要： A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

摘要翻译： 诸如FinFET的半导体器件包括形成在衬底上的多个鳍片和覆盖鳍片的一部分的栅极。 通过外延生长在翅片的侧壁上形成菱形体积，其可以被限制以避免体积的合并或外延体积合并的位置。 由于难以管理菱形体积的合并，钻石形容积的受控合并包括在金刚石体积上沉积非晶半导体材料和结晶过程以将沉积的半导体材料结晶在菱形体上 体积来制造可控和均匀合并的源极漏极。

公开(公告)号：US10083878B1

公开(公告)日：2018-09-25

申请号：US15613474

申请日：2017-06-05

申请人： GLOBALFOUNDRIES INC.

发明人： Brian J. Greene ,  Shreesh Narasimha

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L21/823828 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/12 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

摘要： A self-aligned active region block mask is used to pattern and define a plurality of semiconductor fins as well as attendant shallow trench isolation (STI) structures. The block mask, a portion of which comprises a patterned fin hard mask, permits decoupling of inner and outer fin etch processes, as well as independent optimization of inner fin and outer fin dielectric properties. The fin-forming method also forestalls the creation of isolated, free-standing fins, which decreases the likelihood of mechanical damage to the fins during processing.

公开(公告)号：US09960168B2

公开(公告)日：2018-05-01

申请号：US14582655

申请日：2014-12-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC分类号： H01L21/20 ,  H01L27/108 ,  H01L21/324 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC分类号： H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

摘要： Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

公开(公告)号：US20160190140A1

公开(公告)日：2016-06-30

申请号：US14582655

申请日：2014-12-24

申请人： GLOBALFOUNDRIES Inc.

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC分类号： H01L27/108 ,  H01L21/84 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/311

CPC分类号： H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

摘要： Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

摘要翻译： 公开了用于深沟槽电容器连接的结构和方法。 该结构包括电容器导体的直径减小的顶部。 这增加了相邻深沟槽电容器之间的有效间隔。 然后沉积硅化物或附加的多晶硅以完成深沟槽电容器和相邻晶体管之间的连接。

公开(公告)号：US09991167B2

公开(公告)日：2018-06-05

申请号：US15085077

申请日：2016-03-30

申请人： GLOBALFOUNDRIES INC.

发明人： Arvind Kumar ,  Murshed M. Chowdhury ,  Brian J. Greene ,  Chung-Hsun Lin

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40

CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/381

摘要： Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

公开(公告)号：US09337338B2

公开(公告)日：2016-05-10

申请号：US14820938

申请日：2015-08-07

申请人： GLOBALFOUNDRIES INC.

发明人： Brian J. Greene ,  Yue Liang ,  Xiaojun Yu

IPC分类号： H01L21/338 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L29/7848 ,  H01L21/02112 ,  H01L21/02532 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66568 ,  H01L29/66636

摘要： In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

公开(公告)号：US09305999B2

公开(公告)日：2016-04-05

申请号：US13778419

申请日：2013-02-27

申请人： GLOBALFOUNDRIES INC.

发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L29/06 ,  H01L29/10 ,  H01L29/84 ,  H01L21/762

CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。