Invention Grant
- Patent Title: Power gate for latch-up prevention
- Patent Title (中): 电源门用于防止闩锁
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Application No.: US14331648Application Date: 2014-07-15
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Publication No.: US09311989B2Publication Date: 2016-04-12
- Inventor: Srinivasa Raghavan Sridhara
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Frank D. Cimino
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/417 ; G11C11/412 ; G11C5/14
Abstract:
In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.
Public/Granted literature
- US20160019945A1 POWER GATE FOR LATCH-UP PREVENTION Public/Granted day:2016-01-21
Information query
