Invention Grant
- Patent Title: Integrated circuit package with spatially varied solder resist opening dimension
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Application No.: US14581985Application Date: 2014-12-23
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Publication No.: US09312237B2Publication Date: 2016-04-12
- Inventor: Tieyu Zheng , Sumit Kumar , Sridhar Nara , Renee D. Garcia , Manohar S. Konchady , Suresh B. Yeruva , Lynn H. Chen , Tyler N. Osborn , Sairam Agraharam
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498

Abstract:
An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).
Public/Granted literature
- US20150108204A1 INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION Public/Granted day:2015-04-23
Information query
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