公开(公告)号：US11887962B2

公开(公告)日：2024-01-30

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/30 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11817444B2

公开(公告)日：2023-11-14

申请号：US17587657

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Robert L Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC: H01L25/00 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/11013 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US20220102305A1

公开(公告)日：2022-03-31

申请号：US17032469

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US12243792B2

公开(公告)日：2025-03-04

申请号：US17129135

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoxuan Sun ,  Nitin A. Deshpande ,  Sairam Agraharam

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US12074121B2

公开(公告)日：2024-08-27

申请号：US18128954

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  G01R31/27 ,  H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/544 ,  H01L23/58 ,  H01L23/14 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/585 ,  G01R31/275 ,  H01L22/32 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5385 ,  H01L23/544 ,  H01L24/14 ,  H01L23/147 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/17153 ,  H01L2224/17177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81132 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512 ,  H10B80/00 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

公开(公告)号：US11804470B2

公开(公告)日：2023-10-31

申请号：US16548255

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Xavier F. Brun ,  Kaizad Mistry ,  Paul R. Start ,  Nisha Ananthakrishnan ,  Yawei Liang ,  Jigneshkumar P. Patel ,  Sairam Agraharam ,  Liwei Wang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3675 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/73253

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.

公开(公告)号：US11791274B2

公开(公告)日：2023-10-17

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230197685A1

公开(公告)日：2023-06-22

申请号：US17558995

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Sairam Agraharam

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L21/78 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Microelectronic stacked die package structures formed according to some embodiments may include a first die comprising a first conductive layer over a substrate layer. A second die may be on the first conductive layer. A third die is on the second die. An edge region of the stacked die package structure comprises a first portion over a second portion, the first portion comprising edges of the third die, the second die, and the first conductive layer, and the second portion comprising the substrate layer of the first die, wherein the first portion comprises a curved profile, and the second portion comprises a substantially vertical profile.

公开(公告)号：US10700051B2

公开(公告)日：2020-06-30

申请号：US15996870

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Sairam Agraharam ,  Shengquan Ou ,  Thomas J De Bonis ,  Todd Spencer ,  Yang Sun ,  Guotao Wang

IPC: H01L25/00 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

公开(公告)号：US10461047B2

公开(公告)日：2019-10-29

申请号：US15749744

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan ,  Sairam Agraharam

IPC: H01L23/538 ,  H01L23/58 ,  H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  G01R31/27 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

Abstract: Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semi-conductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.