A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.