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1.发明授权Method of operating memory device and methods of writing and reading data in memory device 有权操作存储器件的方法和在存储器件中写入和读取数据的方法公开(公告)号：US09589674B2
公开(公告)日：2017-03-07
申请号：US14305095
申请日：2014-06-16
发明人： Jong-Pil Son , Young-Soo Sohn , Uk-Song Kang , Chul-Woo Park , Jung-Hwan Choi , Won-Il Bae , Kyo-Min Sohn
CPC分类号： G11C29/52 , G06F11/1048 , G11C2029/0411
摘要： In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.
摘要翻译： 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。
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公开(公告)号：US09519531B2
公开(公告)日：2016-12-13
申请号：US14054957
申请日：2013-10-16
发明人： Seong-Young Seo , Chul-Woo Park
CPC分类号： G06F11/073 , G06F11/076 , G11C7/1006 , G11C7/1063
摘要： In one example embodiment, a memory device includes a cell array configured to receive data at an associated address in response to a write command. The memory device further includes a storage unit configured to receive the associated address and the data in response to the write command and output the data to the associated address of the cell array in response to a rewrite command. The memory device further includes a violation determining unit configured to determine violation data, count a number of the violation data and determine data written to the storage unit as the violation data if a storage duration of the written data is less than a write recovery time (tWR).
摘要翻译： 在一个示例实施例中，存储器设备包括被配置为响应于写入命令在相关联的地址处接收数据的单元阵列。 存储装置还包括存储单元，其被配置为响应于写入命令接收相关联的地址和数据，并且响应于重写命令将数据输出到单元阵列的相关联的地址。 所述存储装置还包括违规判定部，其被配置为如果写入数据的存储持续时间小于写恢复时间，则确定违规数据，对违反数据的数量进行计数，并将写入所述存储单元的数据确定为所述违规数据 tWR）。
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公开(公告)号：US09235466B2
公开(公告)日：2016-01-12
申请号：US13915179
申请日：2013-06-11
发明人： Young-Soo Sohn , Chul-Woo Park , Jong-Pil Son , Jung-bae Lee
CPC分类号： G06F11/1012 , G06F11/10 , G06F11/1024 , G06F11/1048 , G06F11/106 , G11C2029/0411 , H03M13/3707
摘要： An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.
摘要翻译： 纠错装置包括：纠错电路，被配置为对存储器件的多个存储单元的至少一个写入和读出的数据的一部分进行选择性地执行纠错。 数据的部分是从多个存储器单元的子集写入和读出中的至少一个，并且该子集仅包括多个存储器单元中的故障单元。 误差校正装置还包括故障地址存储电路，其被配置为存储故障单元的地址信息。
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公开(公告)号：US09087614B2
公开(公告)日：2015-07-21
申请号：US14087167
申请日：2013-11-22
发明人： Jong-Pil Son , Uk-Song Kang , Chul-Woo Park , Young-Soo Sohn
CPC分类号： G11C29/4401 , G06F11/1048 , G11C5/04 , G11C29/808 , G11C2029/0409 , G11C2029/0411
摘要： In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.
摘要翻译： 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。
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公开(公告)号：US10971942B2
公开(公告)日：2021-04-06
申请号：US15348930
申请日：2016-11-10
发明人： Ku-Chul Jung , Sang-Hyun Ryu , Chul-Woo Park , Sung-Geun Yoon
摘要： An electronic device including: a housing, a battery mounted within the housing, a power interface disposed to or within the housing and configured to receive power from an external power source wirelessly or through a wire, and a circuit configured to electrically connect the battery and the power interface. The circuit includes a first electrical path configured to supply a first part of a current supply from the power interface to the battery, and a second electrical path configured to supply a second part of the current supply from the power interface to the battery and connected to the battery in parallel to the first electrical path. The circuit is configured to selectively control the current supply to the battery via the second electrical path at least partially based on at least one of a charge level of the battery or a signal from a sensor disposed in the housing.
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公开(公告)号：US10199872B2
公开(公告)日：2019-02-05
申请号：US15240516
申请日：2016-08-18
发明人： Ku-Chul Jung , Chul-Woo Park , Sung-Geun Yoon , Sang-Hyun Ryu
摘要： An apparatus for wired and wireless charging of an electronic device are provided. The electronic device includes a housing, a display on a surface of the housing, a battery mounted in the housing, a circuit electrically connected with the battery, a conductive pattern positioned in the housing, electrically connected with the circuit, and configured to wirelessly transmit power to an external device, a connector on another surface of the housing and electrically connected with the circuit, a memory, and a processor electrically connected with the display, the battery, the circuit, the connector, and/or the memory. The circuit is configured to electrically connect the battery with the conductive pattern to wirelessly transmit power to the external device and electrically connect the battery with the connector to transmit power to the external device by wire, simultaneously or selectively, with wirelessly transmitting power to the external device.
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7.发明授权公开(公告)号：US09805827B2
公开(公告)日：2017-10-31
申请号：US14817212
申请日：2015-08-04
发明人： Jong-Pil Son , Chul-Woo Park , Hoi-Ju Chung , Sang-Uhn Cha , Seong-Jin Jang
IPC分类号： G11C11/16 , G11C11/4096 , G11C29/42 , G11C29/44
CPC分类号： G11C29/4401 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4096 , G11C29/42 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.
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公开(公告)号：US09634509B2
公开(公告)日：2017-04-25
申请号：US14534126
申请日：2014-11-05
发明人： Chul-Eun Yun , Ki-Sun Lee , Chul-Woo Park , Ku-Chul Jung , Young-Hee Ha
IPC分类号： H02J7/00
CPC分类号： H02J7/007 , H02J7/0047 , H02J7/0068 , H02J7/34
摘要： A method and an apparatus for rapid charging in an electronic device are provided. In a method for charging a battery of an electronic device, an operation environment of the electronic device is determined. A charging current corresponding to the operation environment of the electronic device is set. Battery charging is started using the set charging current. The battery is charged using a maximum allowed charging current, such that a battery charging time may be reduced.
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公开(公告)号：US09552867B2
公开(公告)日：2017-01-24
申请号：US14588496
申请日：2015-01-02
发明人： Young-Soo Sohn , Uk-Song Kang , Kwang-Il Park , Chul-Woo Park , Hak-Soo Yu , Jae-Youn Youn
IPC分类号： G06F3/06 , G11C11/408 , G11C5/02 , G11C7/02
CPC分类号： G11C11/4087 , G11C5/025 , G11C7/02 , G11C11/4085
摘要： A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.
摘要翻译： 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。
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10.发明授权Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof 有权能够缓解相邻存储单元的干扰的易失性存储器件及其刷新方法公开(公告)号：US09087602B2
公开(公告)日：2015-07-21
申请号：US14219374
申请日：2014-03-19
发明人： Jae-Youn Youn , Su-A Kim , Chul-Woo Park , Young-Soo Sohn
IPC分类号： G11C7/20 , G11C11/406
CPC分类号： G11C11/40615 , G11C7/02 , G11C7/1063 , G11C11/40611 , G11C11/40618
摘要： Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.
摘要翻译： 提供了一种易失性存储器件的刷新方法。 该方法包括：随着对第一存储器区域的访问次数的增加，检测影响第二存储器区域的多个干扰; 当检测到的干扰次数达到参考值时，将来自易失性存储器件的警报信号输出到易失性存储器件的外部; 以及响应于所述警报信号对所述第二存储区域执行刷新操作。
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