公开(公告)号：US20140362637A1

公开(公告)日：2014-12-11

申请号：US14290236

申请日：2014-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui-chul Jeong ,  Sung-hee Lee ,  Dae-sin Kim ,  Seung-hwan Kim ,  Dae-sun Kim ,  Sua Kim ,  Dong-soo Woo ,  Na-ra Kim

IPC: G11C11/4074

CPC classification number: G11C8/08 ,  G11C8/18 ,  G11C11/4085 ,  G11C2029/0411 ,  G11C2207/2227

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract translation: 存储器件包括：存储单元阵列，包括彼此相邻的第一和第二字线，连接到第一字线的第一存储器单元和连接到第二字线并位于第一存储器附近的第二存储器单元 细胞; 以及字线电压提供单元，其响应于第一控制信号将第一字线的字线电压从第一字线电压转换到第二字线电压。 转移控制单元产生用于在从第一字线电压到第二字线电压的转变周期中控制第一字线的字线电压的脉冲的第一控制信号，使得来自 与第二字线电压的第一字线电压与从第二字线电压到第一字线电压的转换波形分布不同。

公开(公告)号：US09318185B2

公开(公告)日：2016-04-19

申请号：US14517255

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua Kim ,  Chul-Woo Park

IPC: G11C11/406 ,  G11C11/408 ,  G11C5/04

CPC classification number: G11C11/4082 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract translation: 存储器模块可以包括m个存储器件。 每个m个存储器件可以被划分为n个区域，每个区域包括对应于行地址的多个行，其中m和n是等于或大于2的整数。一种地址检测器，包括在每个m个存储器件中，其中 对于每个地址检测器，地址检测器可以被配置为在预定时间段内对包括在每个m个存储器件的一个区域中的特定行地址的访问次数进行计数，并且被配置为当 计数访问次数达到参考值。 每个最大计数地址生成器可以被配置为对与其他最大计数地址生成器计数访问的行地址集合不同的一组行地址来计数访问次数。

公开(公告)号：US09747998B2

公开(公告)日：2017-08-29

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua Kim ,  Dongsoo Kang ,  Chulwoo Park ,  Jun Hee Yoo ,  Hak-Soo Yu ,  Jaeyoun Youn ,  Sung Hyun Lee ,  Jinsu Jung ,  Hyojin Choi

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

公开(公告)号：US09348679B2

公开(公告)日：2016-05-24

申请号：US14465105

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

IPC: G06F11/10 ,  G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/44

CPC classification number: G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/78 ,  G11C2029/4402

Abstract: A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

Abstract translation: 提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。 存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。

公开(公告)号：US09293180B2

公开(公告)日：2016-03-22

申请号：US14290236

申请日：2014-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui-chul Jeong ,  Sung-hee Lee ,  Dae-sin Kim ,  Seung-hwan Kim ,  Dae-sun Kim ,  Sua Kim ,  Dong-soo Woo ,  Na-ra Kim

IPC: G11C11/4074 ,  G11C8/08 ,  G11C8/18 ,  G11C11/408 ,  G11C29/04

CPC classification number: G11C8/08 ,  G11C8/18 ,  G11C11/4085 ,  G11C2029/0411 ,  G11C2207/2227

Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.

Abstract translation: 存储器件包括：存储单元阵列，包括彼此相邻的第一和第二字线，连接到第一字线的第一存储器单元和连接到第二字线并位于第一存储器附近的第二存储器单元 细胞; 以及字线电压提供单元，其响应于第一控制信号将第一字线的字线电压从第一字线电压转换到第二字线电压。 转移控制单元产生用于在从第一字线电压到第二字线电压的转变周期中控制第一字线的字线电压的脉冲的第一控制信号，使得来自 与第二字线电压的第一字线电压与从第二字线电压到第一字线电压的转换波形分布不同。