Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices

Invention Grant

US09318552B2 Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices 有权

Title translation: 形成具有较大金属硅化物接触面积的半导体器件的导电接触结构的方法以及所得到的器件

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Patent Title: Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
Patent Title (中): 形成具有较大金属硅化物接触面积的半导体器件的导电接触结构的方法以及所得到的器件
Application No.: US14283404

Application Date: 2014-05-21
Publication No.: US09318552B2

Publication Date: 2016-04-19
Inventor: Ruilong Xie , William J. Taylor, Jr. , Ajey Poovannummoottil Jacob
Applicant: GLOBALFOUNDRIES Inc.
Applicant Address: KY Grand Cayman
Assignee: GLOBALFOUNDRIES Inc.
Current Assignee: GLOBALFOUNDRIES Inc.
Current Assignee Address: KY Grand Cayman
Agency: Amerson Law Firm, PLLC
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/8234 ; H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L29/417 ; H01L29/49

Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices

Abstract:

One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.

Abstract(Chinese):

本文公开的一种说明性方法包括在晶体管器件的源极/漏极区域中形成第一外延半导体材料，第一外延半导体材料在其上表面具有第一横向宽度，形成第二外延半导体材料在所述第一外延半导体材料上以及所述器件的所述侧壁间隔物中的至少一部分栅极帽层或所述侧壁间隔物中的至少一部分，其中所述第二外延半导体材料在其上表面处具有大于第一横向宽度，并且在第二外延半导体材料的上表面上形成金属硅化物区域。

Public/Granted literature

US20150340457A1 METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES FOR A SEMICONDUCTOR DEVICE WITH A LARGER METAL SILICIDE CONTACT AREA AND THE RESULTING DEVICES Public/Granted day:2015-11-26

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS