发明授权
US09324652B2 Method of creating a maskless air gap in back end interconnections with double self-aligned vias
有权
在具有双自对准通孔的后端互连中产生无掩蔽气隙的方法
- 专利标题: Method of creating a maskless air gap in back end interconnections with double self-aligned vias
- 专利标题(中): 在具有双自对准通孔的后端互连中产生无掩蔽气隙的方法
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申请号: US14630572申请日: 2015-02-24
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公开(公告)号: US09324652B2公开(公告)日: 2016-04-26
- 发明人: Manish Chandhok , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L23/522 ; H01L21/768 ; H01L23/532 ; H01L23/535 ; H01L21/3213 ; H01L23/528
摘要:
A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
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