Invention Grant
US09324652B2 Method of creating a maskless air gap in back end interconnections with double self-aligned vias
有权
在具有双自对准通孔的后端互连中产生无掩蔽气隙的方法
- Patent Title: Method of creating a maskless air gap in back end interconnections with double self-aligned vias
- Patent Title (中): 在具有双自对准通孔的后端互连中产生无掩蔽气隙的方法
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Application No.: US14630572Application Date: 2015-02-24
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Publication No.: US09324652B2Publication Date: 2016-04-26
- Inventor: Manish Chandhok , Hui Jae Yoo , Yan A. Borodovsky , Florian Gstrein , David N. Shykind , Kevin L. Lin
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L23/522 ; H01L21/768 ; H01L23/532 ; H01L23/535 ; H01L21/3213 ; H01L23/528

Abstract:
A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.
Public/Granted literature
- US20150171012A1 METHOD OF CREATING A MASKLESS AIR GAP IN BACK END INTERCONNECTIONS WITH DOUBLE SELF-ALIGNED VIAS Public/Granted day:2015-06-18
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