A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.