Invention Grant
US09335368B1 Method and apparatus for quantifying defects due to through silicon VIAs in integrated circuits
有权
用于量化集成电路中通过硅VIA的缺陷的方法和装置
- Patent Title: Method and apparatus for quantifying defects due to through silicon VIAs in integrated circuits
- Patent Title (中): 用于量化集成电路中通过硅VIA的缺陷的方法和装置
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Application No.: US14525596Application Date: 2014-10-28
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Publication No.: US09335368B1Publication Date: 2016-05-10
- Inventor: Luigi Pantisano , Premachandran Chirayarikathuveedu , Rakesh Ranjan , Anil Kumar
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H05K1/02 ; H05K1/03 ; H05K1/11 ; H05K1/18 ; H05K3/40 ; G01R31/26

Abstract:
A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.
Public/Granted literature
- US20160116526A1 METHOD AND APPARATUS FOR QUANTIFYING DEFECTS DUE TO THROUGH SILICON VIAs IN INTEGRATED CIRCUITS Public/Granted day:2016-04-28
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