Invention Grant
US09337119B2 Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
有权
具有高效热路径和相关系统的堆叠式半导体管芯组件
- Patent Title: Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
- Patent Title (中): 具有高效热路径和相关系统的堆叠式半导体管芯组件
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Application No.: US14330900Application Date: 2014-07-14
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Publication No.: US09337119B2Publication Date: 2016-05-10
- Inventor: Sameer S. Vadhavkar , Xiao Li , Jaspreet S. Gandhi
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/34 ; H01L23/31 ; H01L25/065

Abstract:
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.
Public/Granted literature
- US20160013114A1 STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED SYSTEMS Public/Granted day:2016-01-14
Information query
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