公开(公告)号：US11139258B2

公开(公告)日：2021-10-05

申请号：US16782298

申请日：2020-02-05

申请人： MICRON TECHNOLOGY, INC.

发明人： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

摘要： Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US10692733B2

公开(公告)日：2020-06-23

申请号：US16430814

申请日：2019-06-04

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC分类号： H01L21/321 ,  H01L21/768

摘要： Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

公开(公告)号：US10580746B2

公开(公告)日：2020-03-03

申请号：US16102960

申请日：2018-08-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

摘要： Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US20190304799A1

公开(公告)日：2019-10-03

申请号：US16430814

申请日：2019-06-04

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC分类号： H01L21/321 ,  H01L21/768

摘要： Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

公开(公告)号：US20190122950A1

公开(公告)日：2019-04-25

申请号：US16229257

申请日：2018-12-21

申请人： Micron Technology, Inc.

发明人： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijian Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC分类号： H01L23/36 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373 ,  H01L23/42 ,  H01L25/065 ,  H01L25/18

摘要： Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

公开(公告)号：US10262922B2

公开(公告)日：2019-04-16

申请号：US15910136

申请日：2018-03-02

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC分类号： H01L23/46 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

摘要： Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

公开(公告)号：US10163755B2

公开(公告)日：2018-12-25

申请号：US15498321

申请日：2017-04-26

申请人： Micron Technology, Inc.

发明人： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC分类号： H01L21/52 ,  H01L21/54 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/44 ,  H01L25/00 ,  H01L25/18 ,  H01L23/053 ,  H01L23/367 ,  H01L23/373

摘要： Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US10126357B2

公开(公告)日：2018-11-13

申请号：US15660387

申请日：2017-07-26

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Michel Koopmans ,  James M. Derderian

IPC分类号： G01R31/28 ,  G01R1/073

摘要： Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

公开(公告)号：US09741612B2

公开(公告)日：2017-08-22

申请号：US15050858

申请日：2016-02-23

申请人： Micron Technology, Inc.

发明人： Brandon P. Wirz ,  Keith Ypma ,  Christopher J. Gambee ,  Jaspreet S. Gandhi ,  Kevin M. Dowdle ,  Irina Vasilyeva ,  Yang Chao ,  Jon Hacker

IPC分类号： H01L21/768 ,  H01L23/544 ,  H01L21/683 ,  H01L23/48 ,  H01L21/027 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/6836 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature to a through-substrate via includes forming a self-aligned alignment feature having a wall around at least a portion of the TSV and aligning a photolithography tool to the self-aligned alignment feature. In some embodiments, the self-aligned alignment feature is defined by the topography of a seed material at a backside of the device.

公开(公告)号：US20170229439A1

公开(公告)日：2017-08-10

申请号：US15498321

申请日：2017-04-26

申请人： Micron Technology, Inc.

发明人： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC分类号： H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00 ,  H01L23/44 ,  H01L25/18 ,  H01L23/367

CPC分类号： H01L23/44 ,  H01L21/50 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/04 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

摘要： Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.