Invention Grant
- Patent Title: MFENCE and LFENCE micro-architectural implementation method and system
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Application No.: US13838229Application Date: 2013-03-15
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Publication No.: US09342310B2Publication Date: 2016-05-17
- Inventor: Salvador Palanca , Stephen A. Fischer , Subramaniam Maiyuran , Shekoufeh Oawami
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Vecchia Patent Agent, LLC
- Main IPC: G06F15/00
- IPC: G06F15/00 ; G06F9/30 ; G06F9/40 ; G06F9/38

Abstract:
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
Public/Granted literature
- US20130205117A1 MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM Public/Granted day:2013-08-08
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