公开(公告)号：US09342310B2

公开(公告)日：2016-05-17

申请号：US13838229

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Salvador Palanca ,  Stephen A. Fischer ,  Subramaniam Maiyuran ,  Shekoufeh Oawami

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.