A memory device includes a plurality of stacks of alternating active strips and insulating strips. The insulating strips have effective oxide thicknesses (EOT) so that the stacks have non-simple spatial periods on a line through the alternating active strips and insulating strips. A plurality of conductive lines are arranged orthogonally over, and have surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the active strips in the stacks and the conductive lines. Memory elements are disposed in the interface regions, which establish a 3D array of memory cells accessible via the plurality of active strips and the plurality of conductive lines. The insulating strips in the stacks can include a first group of strips having a first EOT and a second group of strips having a second EOT that is greater than the first EOT.