Invention Grant
US09343369B2 Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
有权
三维(3D)集成电路(IC)(3DIC)和相关系统
- Patent Title: Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
- Patent Title (中): 三维(3D)集成电路(IC)(3DIC)和相关系统
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Application No.: US14280731Application Date: 2014-05-19
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Publication No.: US09343369B2Publication Date: 2016-05-17
- Inventor: Yang Du , Karim Arabi
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/822 ; H01L23/528 ; H01L23/522 ; H01L21/768 ; H01L21/50 ; H01L27/06

Abstract:
Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.
Public/Granted literature
- US20150333056A1 METHODS FOR CONSTRUCTING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS Public/Granted day:2015-11-19
Information query
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