Abstract:
Aspects of the disclosure are related to a Lidar device, comprising: a vibrating fiber optic cantilever system on a transmit (TX) path; and a two-dimensional (2D) light sensor array on a receive (RX) path.
Abstract:
Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources.
Abstract:
A light detection and ranging (LIDAR) apparatus includes dual beam scanners with dual beam steering. A first beam scanner in the LIDAR apparatus scans a wider area in one or more of a first plurality of scan patterns, and a second beam scanner in the LIDAR apparatus scans a narrower area in one or more of a second plurality of scan patterns different from the first plurality of scan patterns.
Abstract:
Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.
Abstract:
Systems and methods are directed to a single-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, the dual GSHE-MTJ structure comprising a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter coupled to a second inverter. During a single clock cycle of a clock, a first data value is read out from the slave stage when a clock is in a high state and a second data value is written into the master stage, when the clock is in a low state. The first and second inverters are cross coupled in a latch configuration to hold the first data value as an output, when the clock is in the low state.
Abstract:
A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.
Abstract:
Aspects described herein are related to pipeline circuits employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a pipeline circuit is disclosed. The pipeline circuit includes a first pipeline stage and a second pipeline stage. The first pipeline stage is configured to store a first bit set and to generate a first charge current representing the first bit set. The second pipeline stage includes a first GSHE MTJ element. The first GSHE MTJ element is configured to set a first bit state for the first logical operation, and has a first threshold current level. The first GSHE MTJ element is configured to generate a first GSHE spin current in response to the first charge current. In this manner, the first GSHE MTJ element is also configured to perform the first logical operation on the first bit set.
Abstract:
The systems and method described herein provide efficient wireless communication in a millimeter wave (MMW) phased array system. The system may comprise a plurality of antenna elements, each of the plurality of antenna elements coupled to a transceiver and transceiver having at least one power amplifier. The system may further comprise a gain controller configured to enable or disable the transceivers in response to a power detector output indicating that one or more antenna elements are blocked. Disabling certain transceivers of blocked antenna elements enables the power amplifiers associated with the unblocked antenna elements to continue to operate at maximum efficiency.
Abstract:
Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.
Abstract:
Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C).