Invention Grant
- Patent Title: Solder bump arrangements for large area analog circuitry
- Patent Title (中): 大面积模拟电路的焊接凸块布置
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Application No.: US14071865Application Date: 2013-11-05
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Publication No.: US09343418B2Publication Date: 2016-05-17
- Inventor: Donnacha Lowney , Marites De La Torre , Christopher M. Gorman
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Kevin T. Cuenot
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065
Abstract:
An integrated circuit (IC) can include an analog region of a die of the IC. The analog region includes analog circuitry. The IC further includes a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of the die.
Public/Granted literature
- US20150123265A1 SOLDER BUMP ARRANGEMENTS FOR LARGE AREA ANALOG CIRCUITRY Public/Granted day:2015-05-07
Information query
IPC分类:
