Invention Grant
- Patent Title: Low-latency, frequency-agile clock multiplier
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Application No.: US14565802Application Date: 2014-12-10
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Publication No.: US09344074B2Publication Date: 2016-05-17
- Inventor: Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Charles Shemwell
- Main IPC: H03K5/13
- IPC: H03K5/13 ; H03L7/06 ; H03L7/099 ; H03K5/00 ; H03L7/16

Abstract:
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
Public/Granted literature
- US20150091617A1 LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER Public/Granted day:2015-04-02
Information query
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