Invention Grant
- Patent Title: Reduced stress TSV and interposer structures
- Patent Title (中): 减少应力TSV和插入结构
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Application No.: US14643264Application Date: 2015-03-10
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Publication No.: US09349669B2Publication Date: 2016-05-24
- Inventor: Cyprian Emeka Uzoh , Charles G. Woychik , Terrence Caskey , Kishor V. Desai , Huailiang Wei , Craig Mitchell , Belgacem Haba
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/34 ; H01L21/768 ; H01L23/00 ; H01L23/14 ; H01L23/498
Abstract:
A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.
Public/Granted literature
- US20150187673A1 REDUCED STRESS TSV AND INTERPOSER STRUCTURES Public/Granted day:2015-07-02
Information query
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