Invention Grant
US09349700B2 Semiconductor device and method of forming stress-reduced conductive joint structures
有权
半导体器件及形成应力降低导电接头结构的方法
- Patent Title: Semiconductor device and method of forming stress-reduced conductive joint structures
- Patent Title (中): 半导体器件及形成应力降低导电接头结构的方法
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Application No.: US14223695Application Date: 2014-03-24
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Publication No.: US09349700B2Publication Date: 2016-05-24
- Inventor: Ming-Che Hsieh , Chien Chen Lee
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31
Abstract:
A semiconductor device has a substrate. A first conductive layer is formed over the substrate. A first insulating layer is formed over the substrate. A second insulating layer is formed over the first insulating layer. A second conductive layer is formed over the second insulating layer. The second insulating layer is formed to include a cylindrical shape. The second conductive layer is formed as an under bump metallization layer. A first opening is formed in the second insulating layer. A second opening is formed in the second insulating layer around the first opening in the second insulating layer. An opening is formed in the first insulating layer over the first conductive layer. An opening is formed in the second insulating layer over the first conductive layer with the opening of the first insulating layer being greater than the opening of the second insulating layer.
Public/Granted literature
- US20140319695A1 Semiconductor Device and Method of Forming Stress-Reduced Conductive Joint Structures Public/Granted day:2014-10-30
Information query
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