Invention Grant
- Patent Title: Modular and scalable cyclic redundancy check computation circuit
- Patent Title (中): 模块化和可扩展的循环冗余校验计算电路
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Application No.: US13841574Application Date: 2013-03-15
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Publication No.: US09350385B2Publication Date: 2016-05-24
- Inventor: Weirong Jiang , Gordon J. Brebner , Mark B. Carson
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Kin-Wah Tong; Diana J. Rea
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/00 ; H03M13/09
Abstract:
Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.
Public/Granted literature
- US20140281844A1 MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT Public/Granted day:2014-09-18
Information query
