公开(公告)号：US20200293635A1

公开(公告)日：2020-09-17

申请号：US16299575

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Brian S. Martin ,  Premduth Vidyanandan ,  Mark B. Carson ,  Neil Watson ,  Gary J. McClintock

IPC: G06F21/12 ,  G06F21/57 ,  H04L9/32 ,  H04L9/30 ,  G06F9/50

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

公开(公告)号：US11443018B2

公开(公告)日：2022-09-13

申请号：US16299575

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Brian S. Martin ,  Premduth Vidyanandan ,  Mark B. Carson ,  Neil Watson ,  Gary J. McClintock

IPC: G06F21/12 ,  G06F21/57 ,  H04L9/32 ,  G06F9/50 ,  H04L9/30

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a programmable fabric of the programmable device, and an intellectual property (IP) checker circuit in the kernel logic. The IP checker circuit is configured to obtain a device identifier (ID) of the programmable device and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

公开(公告)号：US20200293636A1

公开(公告)日：2020-09-17

申请号：US16299611

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Brian S. Martin ,  Premduth Vidyanandan ,  Mark B. Carson ,  Neil Watson ,  Gary J. McClintock

IPC: G06F21/12 ,  G06F21/57 ,  H04L9/32 ,  H04L9/30 ,  G06F9/50

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

公开(公告)号：US11294992B2

公开(公告)日：2022-04-05

申请号：US16299611

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Brian S. Martin ,  Premduth Vidyanandan ,  Mark B. Carson ,  Neil Watson ,  Gary J. McClintock

IPC: G06F21/12 ,  G06F21/57 ,  H04L9/32 ,  G06F9/50 ,  H04L9/30

Abstract: An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.

公开(公告)号：US09350385B2

公开(公告)日：2016-05-24

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。

公开(公告)号：US20140281844A1

公开(公告)日：2014-09-18

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。