发明授权
- 专利标题: Power efficient processor architecture
- 专利标题(中): 高效的处理器架构
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申请号: US13992361申请日: 2011-09-06
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公开(公告)号: US09360927B2公开(公告)日: 2016-06-07
- 发明人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
- 申请人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadogopan Srinivasan , Jaideep Moses , Srihari Makineni
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop, Pruner & Hu, P.C.
- 国际申请: PCT/US2011/050580 WO 20110906
- 国际公布: WO2013/036222 WO 20130314
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F9/50
摘要:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
公开/授权文献
- US20130262902A1 POWER EFFICIENT PROCESSOR ARCHITECTURE 公开/授权日:2013-10-03
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