A display driver integrated circuit is provided which includes a first line buffer which receives first pixel data of an odd lane in response to an external clock and outputs the first pixel data in response to an internal clock; a second line buffer which receives second pixel data of an even lane in response to the external clock and outputs the second pixel data in response to the internal clock; a line buffer controller which receives display data by the two pixel data to output the first and second pixel data; a data merger which merges the first pixel data output from the first line buffer and second pixel data output from the second line buffer; and an image data processing block which processes the merged pixel data, wherein a frequency of the internal clock is lower than a frequency of the external clock.