Invention Grant
- Patent Title: Chip package and fabrication method thereof
- Patent Title (中): 芯片封装及其制造方法
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Application No.: US14465015Application Date: 2014-08-21
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Publication No.: US09362134B2Publication Date: 2016-06-07
- Inventor: Chia-Sheng Lin
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/311 ; H01L21/02 ; H01L21/768 ; H01L23/31 ; H01L23/48 ; H01L23/525 ; H01L31/02 ; H01L31/0232 ; H01L27/146 ; H01L31/18 ; H01L23/00 ; H01L33/58 ; H01L33/62
Abstract:
A fabrication method of a chip package includes the following steps. A wafer structure having a wafer and a protection layer is provided. The first opening of the wafer is aligned with and communicated with the second opening of the protection layer. A first insulating layer having a first thickness is formed on a conductive pad exposed from the second opening, and a second insulating layer having a second thickness is formed on a first sidewall of the protection layer surrounding the second opening and a second sidewall of the wafer surrounding the first opening. The first and second insulating layers are etched, such that the first insulating layer is completely removed, and the second thickness of the second insulating layer is reduced.
Public/Granted literature
- US20150041995A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF Public/Granted day:2015-02-12
Information query
IPC分类:
