Invention Grant
- Patent Title: Source line formation in 3D vertical channel and memory
- Patent Title (中): 三维垂直通道和存储器中的源极线形成
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Application No.: US14608053Application Date: 2015-01-28
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Publication No.: US09362302B1Publication Date: 2016-06-07
- Inventor: Erh-Kun Lai
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Yiding Wu
- Main IPC: G11C16/04
- IPC: G11C16/04 ; H01L27/115 ; G11C16/28 ; H01L29/06 ; H01L29/45 ; H01L21/311 ; H01L21/3213 ; H01L21/28

Abstract:
A memory device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom level of conductive strips, a plurality of intermediate levels of conductive strips, and a top level of conductive strips. A reference conductor is disposed in a level between the bottom level of conductive strips and a substrate, isolated from the substrate by a layer of insulating material, and isolated from the bottom level by another layer of insulating material. A plurality of vertical active strips is disposed between the plurality of stacks in electrical contact with the substrate, and with the reference conductor. Charge storage structures are disposed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate levels and the vertical active strips. A bias circuit is configured to provide different bias arrangements to the reference conductor and the substrate.
Information query