Invention Grant
- Patent Title: Reduction of forming voltage in semiconductor devices
-
Application No.: US14595421Application Date: 2015-01-13
-
Publication No.: US09362497B2Publication Date: 2016-06-07
- Inventor: Pragati Kumar , Tony P. Chiang , Prashant B Phatak , Yun Wang
- Applicant: Intermolecular Inc.
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L45/00
- IPC: H01L45/00 ; G11C13/00 ; H01L27/24

Abstract:
This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.
Public/Granted literature
- US20150137064A1 Reduction of forming voltage in semiconductor devices Public/Granted day:2015-05-21
Information query
IPC分类: