An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.