公开(公告)号：US09378162B2

公开(公告)日：2016-06-28

申请号：US13898816

申请日：2013-05-21

Applicant: ARM LIMITED

Inventor： Anthony Jebson ,  Andrew John Turner ,  Matthew Lucien Evans ,  Gareth James Evans ,  Adam James McNeeney

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45533 ,  G06F9/4812

Abstract: An interrupt controller for controlling the routing and handling of interrupts received at a data processing apparatus including at least one physical processing unit configured to run at least one of a plurality of virtual processors and a memory. The interrupt controller includes redistribution circuitry with at least one data store corresponding to the unit, the data store storing a pointer to a virtual pending table storing currently pending virtual interrupts for a virtual processor currently running on the corresponding unit and a pointer to a pending table configured to store currently pending physical interrupts for the corresponding unit and an input configured to receive a virtual interrupt for interrupting a virtual processor. Control circuitry is configured to add the virtual interrupt to the virtual pending table and to store the virtual interrupt in the virtual pending table for the virtual processor that is stored in the memory.

Abstract translation: 一种中断控制器，用于控制在包括至少一个物理处理单元的数据处理装置处接收的中断的路由和处理，所述物理处理单元被配置为运行多个虚拟处理器和存储器中的至少一个。 中断控制器包括具有与单元对应的至少一个数据存储器的再分配电路，数据存储器存储指向虚拟挂起表的指针，该虚拟挂起表存储当前在相应单元上运行的虚拟处理器的当前待处理的虚拟中断，以及指向待处理表的指针 被配置为存储用于相应单元的当前待处理的物理中断，以及被配置为接收用于中断虚拟处理器的虚拟中断的输入。 控制电路被配置为将虚拟中断添加到虚拟挂起表并将虚拟中断存储在存储在存储器中的虚拟处理器的虚拟挂起表中。

公开(公告)号：US10853071B2

公开(公告)日：2020-12-01

申请号：US16203886

申请日：2018-11-29

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Gareth James Evans

IPC: G06F9/30 ,  G06F9/455

Abstract: A method and apparatus for simulating target program code on a host data processing apparatus, the simulation mapping load-exclusive instructions in the target program code to load instructions, and mapping store-exclusive instructions in the target program code to compare-and-swap instructions.

公开(公告)号：US10423537B2

公开(公告)日：2019-09-24

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/1036 ,  G06F12/02

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.

公开(公告)号：US20190236019A1

公开(公告)日：2019-08-01

申请号：US15884526

申请日：2018-01-31

Applicant: Arm Limited

Inventor： Adam James McNeeney ,  Matthew Lucien Evans

IPC: G06F12/1009 ,  G06F12/02 ,  G06F12/1036 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/0215 ,  G06F12/1036 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/68

Abstract: A method is provided for controlling processing of target program code on a host data processing apparatus to simulate processing of the target program code on a target data processing apparatus. In response to a target memory access instruction of the target program code specifying a target address within a simulated address space having a larger size than a host address space supported by a memory management unit of the host data processing apparatus, an address space resizing table is looked up to map the target address to a transformed address within said host address space, and information is generated for triggering a memory access based on translation of the transformed address by the memory management unit of the host data processing apparatus.